This invention relates to a semiconductor memory device in which memory cells are allocated with successive addresses.
A conventional semiconductor memory device has a structure such as shown in, for example, FIG. 1. In the memory device shown in FIG. 1, row decoder 11 selects one of a plurality of row lines 12 according to a row address signal. Column decoder 13 selects one of a plurality of selecting lines 14 for selecting one of a plurality of column lines 16 according to a column address signal. When one selecting line 14 is selected, transistor 15, whose gate is connected to the selected selecting line 14, is turned on and column line 16, to which the selected transistor 15 is provided, is selected. When one row line 12 and one column line 16 are selected, memory cell 18, which is located at the cross point of the selected row line 12 and column line 16, is selected. Data is then read out of the selected memory cell 18.
In the conventional semiconductor memory device, row lines 12 are made of polysilicon. This gives large resistances to row lines 12. Furthermore, a plurality of memory cells 18 are connected to row lines 12, giving large capacitances to row lines 12 and thereby, in combination with the resistance factor, providing row lines 12 with heavy loads. Consequently, the time period required from when a row address signal is changed to when data is read out of the selected memory cell 18 to a selected column line 16, is significantly longer than the time period required from when a column address signal is changed to when the column line 16 is selected, so much so, in fact, that the time taken by a sense amplifier for sensing data is unsatisfactorily long. This is particularly so in a semiconductor memory device in which data is successively read out of memory cells which are allocated with successive addresses.